Research Thesis

M.Sc. Research Thesis

  1. Design for Testability in the Presence of Asymmetric Transistor Aging
  2. Adaptive aging timing margins optimized for power saving 
  3. Compression of AI transformer models for specialized tasks
  4. Exploration of power integrity reliability concerns in modern VLSI Technologies.
  5. Physical Design Flow optimized by Machine Learning models

 

M.Sc. Research with option to Ph.D.

  1. Approximated computing architecture for Advanced Machine Learning and Generative AI models
  2. Asymmetric Aging induced by Hot Carrier Injection - characterization study and mitigation approaches
  3. A RISCV based Systolic array accelerator for ML applications

 

Ph.D. Research 

  1. Asymmetric-aging aware Design for Testability (DFT) flow
  2. Design Flow optimization for chiplets
  3. Physical Design Flow optimized by Machine Learning models