1. Advanced VLSI Process Node Reliability Challenges: The shrinking dimensions of advanced VLSI process nodes into nanometric scales introduce significant reliability challenges related to the aging of integrated circuits. This aging process results not only in performance degradation but also in incorrect functionality over the lifetime of the circuits. In this research domain, I examine two dominant reliability phenomena: transistor aging and electromigration. Transistor aging is a physical deterioration process that occurs over the transistor's lifetime, while electromigration is the wearing out of metal interconnects. Two physical mechanisms govern transistor aging which are illustrated in Figure 1: HCI (Hot Carrier Injection) and BTI (Bias Temperature Instability). HCI occurs when high kinetic current flows through a transistor, whereas BTI occurs when a static voltage (logical state) is applied to the gate of a transistor without current flow for an accumulated long period, typically ranging from 10s to several weeks. Both BTI and HCI increase the transistor threshold voltage, which increases the switching delay. As part of this research, we have introduced novel micro-architectural and physical design flow solutions to mitigate these challenging phenomena. Additionally, we have developed a new chip design methodology, illustrated in the figure below, that aims mitigating transistor aging concerns.

 

Our next steps as part of this research aims to broaden the previous works on asymmetric transistor aging. Through this research, we will cover aspects of asymmetric aging related to new multiple disciplines, including frontend design, DFT, backend, product engineering, and test engineering. The research focus will primarily be on both pre-silicon and post-silicon related aspects. The pre-silicon stage includes the research and development of the following activities: 

a. Expand the study on asymmetric transistor aging to include hot carrier injection phenomenon which has not been studies in my previous and current research.  

b. A backend methodology to handle asymmetric aging in the implementation and signoff flows.  

c. A design methodology for prevention of asymmetric aging. Several techniques for preventions have been successfully introduced in my past research works, however there is a need to expand these approaches to advanced process nodes.   

d. Chip-health monitoring agents which will be integrated into the chip in critical chip elements to measure reliability degradation. Such monitors include: 

e. Asymmetric-aging aware DFT flow that extends current DFT flows aiming at: 

1. Allow at-speed ATPG testing to incorporate asymmetric aging effect. 

2. Enable HTOL testing in mission profile conditions that represent the IC deployment in the field. 

As part of the research proposal, we will manufacture a test chip in an advanced process node to serve as a proof-of-concept (POC) for the pre- and post-silicon methodologies developed in this research.  
This research will be done in collaboration with leading Hi-Tech companies. 

 

2. VLSI design flow: 

a. Research on the new design challenges introduces by advanced process nodes (5nm, 3nm, 2nm). The research will introduce new approaches to facilitate the process challenges and new EDA tools and flows. Through the research I also intend to collaborate with VLSI foundries: TSMC and GF.

b. Explore machine learning technique to optimized VLSI design implementation flow.

3. VLSI Design of ML accelerators 

a. Continue the research and development of innovative domain specific for various fields: systolic arrays, GPUs, transformers and others.  

b. Research on the VLSI implementation aspects of machine learning models for specialized tasks.  

c. Design of memory systems for ML accelerators. Large language models, like transformer present unprecedented requirements for huge memory bandwidth which become the bottleneck of such system. This introduces a significant research challenge to explore different innovative paths to optimize such model’s bandwidth requirements.   

4. Computer Architecture 

Continue developing the Massive Simultaneous Multi-Threading (MSMT) architecture. As part of this research, we identified that memory system introduces a major bottleneck. Our initial observations call for revising the existing memory subsystem of modern microprocessor to incorporate elasticity to allow different threads utilize dynamic and adaptive resource allocation.  

5. Machine Learning 

a. Continue the research work of new algorithm for neural networks for specialized tasks. I intend to extend the prior work and enhance it with reinforcement learning model. 

b. Exploration of new algorithms for machine learning model compression and computational optimization.